1. Field of the Invention
The present invention relates to the field of semiconductor circuit manufacturing, and more specifically, to a method of forming an electrical connection between conductive layers of a semiconductor device.
2. Description of Relevant Art
Integrated circuits are made up of literally millions of active devices formed in or on a silicon substrate or well. The active devices are interconnected together in order to form functional circuits and components from the devices. The devices are interconnect together through the use of multilevel interconnects. A cross-sectional illustration of a typical multilevel interconnect structure 100 is shown in FIG. 1. Interconnect structures normally have a first level of metallization or interconnect layer 102 (typically aluminum alloys or tungsten), a second level of metallization 104 and sometimes a third or even fourth level of metallization. Interlevel dielectrics 106 (ILDs) such as silicon dioxide (SiO.sub.2) are used to electrically isolate different levels of metallization and silicon substrate or well 108. The electrical connections between different interconnect levels are made through the use of metalized vias 110 formed in ILD 106. In a similar manner, metal contacts 112 are used to form electrical connections between interconnect levels and devices formed in well 108. The metal vias 110 and contacts 112, herein after being commonly referred to as "vias", are generally filled with tungsten 114 and generally have a titanium nitride (TiN) barrier layer 116. Titanium nitride barrier layer 116 provides an adhesion layer for tungsten metal 114. It is to be appreciated that tungsten exhibits poor adhesion to materials such as oxides, metals, silicon, and silicides.
A problem with metalized vias 110 and 112 is that the titanium nitride (TiN) adhesion layer is formed by sputtering. Sputter processes classically exhibit poor step coverage 118 as shown in FIG. 1. Poor step coverage in vias translates into reliability (open circuits) and performance (increased resistance) problems for the interconnect structure. Step coverage becomes worse and reaches an unacceptable level as via dimensions decrease in order to facilitate higher density circuits. The problem is especially compounded when small dimensioned vias with vertical side walls are formed. Sputtered titanium nitride barrier layers can only be reliably used in vias with aspect ratios less than about 3.0. Sputtered titanium nitride barrier layers are incompatible with future ultra large scale integrated (ULSI) circuits which will require vias with aspect ratios &gt;4.0.
A chemical vapor deposited (CVD) titanium nitride adhesion layer has been suggested as a substitute for the sputtered titanium nitride adhesion layer. CVD processes generally exhibit better step coverage than do sputter processes. Unfortunately, CVD titanium nitride requires a TiCl.sub.4 high temperature process (700.degree. C.). Such a high temperature process is incompatible with some layers utilized in multilevel metallization schemes. Additionally, chlorine from TiCl.sub.4 can be incorporated into the barrier layer and detrimentally affect its quality. Still further, CVD titanium nitride is a relatively new and untested process which requires new and elaborate machinery.
As an alternative to titanium nitride adhesion layers, tungsten silicide (WSi.sub.x) adhesion layers have been proposed. Unfortunately, a tungsten via formed with a tungsten silicide adhesion layer suffers from "etch out" as shown in FIG. 2. (See "Underlying Dependence Of Thin Film Stresses In Blanket CVD Tungsten", Tungsten and Other Refractory Metals for VLSI Applications III; Published by Materials Research Society: 1988, pgs. 407-414.) That is, presently there is no plasma etch chemistry which can be used to etch back the tungsten layer which does not preferentially attack the tungsten silicide adhesion layer and cause etch out. If the adhesion layer is etched away, the tungsten metal can "pop out" and cause a failure. Another problem with the plasma etchback process shown in FIG. 2 is that the tungsten metals 204 can become recessed into the via hole during etchback. Such a recessed plug can adversely effect the planarization of subsequently formed interconnect layers. Thus, the use of a tungsten via in conjunction with a tungsten silicide adhesion layer is presently an unreliable process.
Thus, what is desired is a method of forming a reliable tungsten plug which can be used in modem, high density, multilevel integrated circuits.